1. Field of the Invention
The present invention relates to shift register circuits configured only by field effect transistors of the same conductivity type used in scanning line driving circuit and the like of the image display apparatus etc., in particular, to a bi-directional shift register in which the direction of shifting the signal can be reversed.
2. Description of the Background Art
In the image display apparatus (hereinafter referred to as “display apparatus”), such as a liquid crystal display apparatus, a gate line (scanning line) is arranged for each pixel row (pixel line) of a display panel in which a plurality of pixels are arrayed in a matrix form, and the gate line is sequentially selected and driven at a cycle of one horizontal period of the display signal to update the displayed image. A shift register for performing the shift operation that completes the round in one frame period of the display signal is used for the gate line driving circuit (scanning line driving circuit) to sequentially select and drive the pixel line, that is, the gate line.
The shift register used in the gate line driving circuit is desirably configured only by the field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display apparatus. Various shift registers configured only by the field effect transistors of N-type or P-type and display apparatuses mounted with the same are proposed. MOS (Metal Oxide Semiconductor) transistor and TFT (Thin Film Transistor) etc. are used as the field effect transistor.
The gate line driving circuit is configured by the shift register comprising a plurality of stages. That is, the gate line driving circuit is configured by cascade connecting a plurality of shift register circuits arranged for every pixel line, that is, every gate line. In the present specification, each of the plurality of shift register circuits configuring the gate line driving circuit is referred to as “unit shift register” for the sake of convenience of the explanation.
In a liquid crystal display apparatus of matrix type in which the liquid crystal pixels are arranged in a matrix form, for example, the request to change the display pattern such as inverting the displayed image upside down or mirror reversing the same and changing the displaying order when displaying is often made.
The display inversion is desired, for example, when applying the liquid crystal display apparatus to an OHP (Overhead Projector) projection apparatus, and using a translucent screen. This is because, when the translucent screen is used, the picture on the screen is inverted as opposed to when projecting the picture from the front side of the screen since the picture is projected from the back side of the screen when seen from the viewer. The change in displaying order is desired when rendition effect is desired in displaying a bar graph, histogram etc. such as gradually appearing the displaying image from the top to the bottom or vice versa, that is, gradually appearing from the bottom to the top.
One method of performing display pattern change of such display apparatus includes switching the shift direction of the signal in the gate line driving circuit. The shift register (hereinafter referred to as “bi-directional shift register”) in which the shift direction of the signal can be switched is thus proposed.
For example, the unit shift register (hereinafter also referred to as “bi-directional unit shift register”) used in the bi-directional shift register configured only by the field effect transistors of N-channel type is disclosed in FIG. 13 of Japanese Patent Application Laid-Open No. 2001-350438 below (similar circuit is shown in FIG. 3 of the present specification, where the reference number in parentheses below correspond to those in FIG. 3).
The output stage of the unit shift register is configured by a first transistor (Q1) for providing a clock signal (CLK) input to a clock terminal (CK) to an output terminal (OUT), and a second transistor (Q2) for supplying a reference voltage (VSS) to the output terminal. A gate node (N1) of the first transistor is defined as the first node, and a gate node (N2) of the second transistor is defined as the second node.
The unit shift register includes a third transistor (Q3) for providing a first voltage signal (Vn) to the first node based on the signal input to a predetermined first input terminal (IN1), and a fourth transistor (Q4) for providing a second voltage signal (Vr) to the first node based on the signal input to a predetermined second input terminal (IN2). The first and second voltage signals are signals complementary to each other where when one of the voltage level (hereinafter referred to simply as “level”) is H (High), the other voltage level is L (Low) level.
The first transistor is driven by the third and fourth transistors. The second transistor is driven by an inverter (Q6, Q7) having the first node as an input end and a second node as an output end. In other words, when the relevant unit shift register outputs the output signal, the first node is at H level due to the operation of the second and third transistors, and the second node is accordingly at L level due to the inverter. The first transistor is thereby turned ON, the second transistor is turned OFF, and the clock signal is transmitted to the output terminal in such state, whereby the output signal is output. If the output signal is not output, on the other hand, the first node is at L level due to the operation of the second and third transistors, and the second node is accordingly at H level due to the inverter. The first transistor is thereby turned OFF, the second transistor is turned ON, and the voltage level of the output terminal is maintained at L level.
If the first voltage signal is at H level and the second voltage signal is at L level, for example, the first node becomes H level and the second node accordingly becomes L level when the signal is input to the first input terminal, whereby the first transistor is turned ON and the second transistor is turned OFF. Therefore, the output signal is output from the relevant unit shift register at a timing the clock signal is subsequently input. In other words, when the first voltage signal is at H level and the second voltage signal is at L level, the relevant unit shift register operates to output the signal input to the first input terminal in a temporally shifted manner.
On the other hand, if the first voltage signal is at L level and the second voltage signal is at H level, the first node becomes H level and the second node accordingly becomes L level when the signal is input to the second input terminal, whereby the first transistor is turned ON and the second transistor is turned OFF. Therefore, the output signal is output from the relevant unit shift register at a timing the clock signal is subsequently input. In other words, when the first voltage signal is at L level and the second voltage signal is at H level, the relevant unit shift register operates to output the signal input to the second input terminal in a temporally shifted manner.
The bi-directional unit shift register of FIG. 13 of Japanese Patent Application Laid-Open No. 2001-350438 (FIG. 3 of the present specification) switches the shift direction of the signal by switching the levels of the first voltage signal and the second voltage signal for driving the first transistor.
A first problem of the conventional bi-directional shift register will be described first. When configuring the gate line driving circuit by cascade connecting the conventional bi-directional unit shift registers, the output signal of the previous stage is input to the first input terminal (IN1) of the unit shift register of each stage, and the output signal of the next stage is input to the second input terminal (IN2) (see FIG. 2 of the present specification). The output signal (gate line driving signal) is output only during one specific horizontal period within one frame period from the respective unit shift register, and is not output during other periods since the gate line driving circuit operates to sequentially select each gate line at a cycle of one frame period. Therefore, the third and fourth transistors (Q3, Q4) driving the first transistor (Q1) are turned OFF most of the time during one frame period in each unit shift register.
In the conventional unit shift register, the gate of the first transistor, that is, the first node (N1) is in the floating state when the third and fourth transistors are turned OFF. In particular, the period (non-selective period) in which the output signal is not output continues for a length of about one frame period, during which period, the first node is maintained at L level of floating state, and the first transistor is maintained in the OFF state. If leakage current is generated in the third transistor (when first voltage signal is at H level) or the fourth transistor (when second voltage signal is at H level), the charges involved therewith accumulates at the first node in the floating state, and the potential of the first node gradually rises.
Furthermore, the clock signal is continuously input to the clock terminal (CK) (drain of first transistor) even during the non-selective period, and the potential of the first node rises while the clock signal is at H level due to coupling via overlapping capacity between drain and gate of the first transistor.
When the potential of the first node rises by the leakage current and the clock signal, the problem of malfunction arises in which the first transistor that is to be turned OFF is turned ON, and the gate line is unnecessarily activated when the voltage between the gate and the source of the first transistor exceeds a threshold voltage. When a pixel switch element (active transistor) arranged on each pixel is turned ON, the data in the pixel is re-written, and display defect occurs.
Next, a second problem will be described. The first node (N1) is at H level of the floating state and the first transistor (Q1) is maintained in the ON state during the period (selective period) the bi-directional unit shift register outputs the output signal. When the clock signal of the clock terminal (CK) (drain of first transistor) becomes H level, the output terminal (OUT) becomes H level following thereto, and the gate line is activated. In this case, the first node is boosted while the clock signal is at H level due to coupling via the drain-gate overlapping capacity, the gate-channel capacity, and the gate-source overlapping capacity of the first transistor. The boost of the first node increases the driving ability (ability to flow current) of the first transistor, whereby the relevant unit shift register charges the gate line at high speed.
However, when the first node is boosted, high voltage is applied between the drain and the source of the third transistor (Q3) (when first voltage signal is at L level) or the fourth transistor (Q4) (when second voltage is at L level), and thus the leakage current tends to be easily generated depending on the voltage resistance property of between the drain and the source. When the level of the first node lowers due to the leakage current, the driving ability of the first transistor lowers, and the falling speed of the output signal of when the clock signal returns from H level to L level becomes slower. If the turning OFF of the pixel transistor is delayed, the data in the pixel may be re-written on the data of the next line, and display failure may occur.
A third problem will be described. In the gate line driving circuit configured by the conventional bi-directional shift register, a control pulse referred as “start pulse” corresponding to the head of each frame of the image signal is input as input signal to the first input terminal (IN1) of the unit shift register of the leading stage in the case of forward shift of shifting the signal in the direction of the previous stage to the subsequent stage and the like. The input signal is sequentially transmitted to each cascade connected unit shift register to the unit shift register of the final stage. In the conventional bi-directional shift register, a control pulse referred to as “end pulse” corresponding to the end of each frame period of the image signal must be input to the second input terminal (IN2) of the final stage immediately after the unit shift register of the final stage outputs the output signal. Otherwise, the first transistor of the final stage cannot be turned OFF, and the output signal continues to be output from the final stage.
In the case of a normal shift register for shifting the signal only in one direction, the end pulse is less likely to become necessary and is sufficiently with the start pulse since a dummy stage is further arranged in the next stage after the final stage and the output signal thereof is used as the end pulse, or the clock signal having a phase different from the clock signal input to the final stage is used as the end pulse. Therefore, most of the drive controlling devices for controlling the operation of the normal gate line driving circuit for shifting the signal (gate line driving signal) only in one direction output only the start pulse.
In the case of the bi-directional shift register, however, the start pulse must be input in the reverse shift to shift the signal in the direction of subsequent stage to previous stage in addition to inputting the end pulse to the second input terminal of the final stage. Furthermore, it is not as simple as with shifting in only one direction since the output signal of the dummy stage may become the wrong start pulse when the shift direction is reversed, if the dummy stage is simply arranged. Therefore, the drive controlling device of the gate line driving circuit for shifting the signal in bi-direction mounted with the output circuit of not only the start pulse but also of the end pulse is adopted, which increases the cost of the drive controlling device, that is, increases the cost of the display apparatus.
A fourth problem will now be described. When the bi-directional shift register is in the selective period as described above, the first node (N1) is at H level, the second node (N2) is at L level, and thus the first transistor (Q1) is turned ON and the second transistor (Q2) is turned OFF. In the forward shift, the first node becomes L level and the first transistor is turned OFF when the output signal of the next stage is input to the second input terminal (IN2) in transitioning from the selective period to the non-selective period. Accordingly, the second node becomes H level by the inverter (Q6, Q7) in the unit shift register, and the second transistor is turned ON.
The parasitic capacity exists between the gate line and the data line of the display panel, and the voltage change of the data line might be added as noise to the gate line, that is, the output terminal (OUT) of the unit shift register due to coupling therethrough. If the second transistor is not sufficiently turned ON in this case, the charges involved in the noise cannot be discharged from the output terminal, whereby the pixel transistor turns ON, and the wrong data may be written to the pixel. Therefore, the potential of the second node (gate of the second transistor) is preferably raised at high speed when transitioning to the non-selective period. To this end, the on-resistance of the transistors (Q6, Q7) configuring the inverter is lowered. However, since the relevant inverter is a ratio type inverter configured by the field effect transistors of the same conductivity type, the pass through current flowing through the inverter when the output of the inverter is at L level increases and the power consumption increases if the on-resistance of the transistor is lowered.